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HANBit
HAN BIT
HMS1M32M8V
SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V Part No.
HMS1M32M8V, HMS1M32Z8V
GENERAL DESCRIPTION
The HMS1M32M8V is a high-speed static random access memory (SRAM) module containing 1,048,576 words organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 72-pin, doublesided, FR4-printed circuit board. PD0 to PD3 identify the module's density allowing interchangeable use of alternate density, industry- standard modules. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module's 4 bytes independently. Output enable (/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +3.3V DC power supply and all inputs and outputs are fully LVTTL-compatible.
FEATURES
Part identification
- HMS1M32M8V : SIMM design - HMS1M32Z8V : ZIP design Pin-Compatible with the HMS1M32M8V
PIN ASSIGNMENT
NC NC PD2 PD3 Vss PD0 PD1 DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 Vcc A0 A7 A1 A8 A2 A9 DQ12 DQ4 DQ13 DQ5 DQ14 DQ6 DQ15 DQ7 Vss /WE A15 A14 /CE2 /CE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 /CE4 /CE3 A17 A16 /OE Vss DQ24 DQ16 DQ25 DQ17 DQ26 DQ18 DQ27 DQ19 A3 A10 A4 A11 A5 A12 Vcc A13 A6 DQ20 DQ28 DQ21 DQ29 DQ22 DQ30 DQ23 DQ31 Vss A18 A19 NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Fast access times : 10, 12ns and 15ns High-density 4MByte design High-reliability high-speed design Single + 3.3V 0.3V power supply Easy memory expansion /CE and /OE functions All inputs and outputs are LVTTL-compatible Industry-standard pinout FR4-PCB design Low power Dissipation
OPTIONS
Timing
10ns access 12ns access 15ns access
MARKING
-10 -12 -15
Packages
72-pin SIMM M
SIMM TOP VIEW
PD0 = Vss PD1 = Open PD2 = Vss PD3 = Open
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HANBit FUNCTIONAL BLOCK DIAGRAM
32 20 A0-19 DQ 0-3 /WE /OE /WE
HMS1M32M8V
DQ0 - DQ31 A0 - A19
A0-19 DQ 4-7 /OE
U1
/CE
U5
/CE
/CE1 A0-19 DQ 8-11 /WE /OE /WE A0-19 DQ12-15 /OE
U2
/CE
U6
/CE
/CE2 A0-19 DQ16-19 /WE /OE /WE A0-19 DQ20-23 /OE
U3
/CE
U7
/CE
/CE3 A0-19 /WE /OE DQ24-27 /WE /OE /WE A0-19 DQ28-31 /OE
U4
/CE
U8
/CE
/CE4
MODE STANDBY NOT SELECTED READ WRITE
/OE X H L X
/CE H L L L
/WE X H H L
OUTPUT HIGH-Z HIGH-Z Dout Din
POWER STANDBY ACTIVE ACTIVE ACTIVE
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HANBit ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN,OUT VCC PD TSTG
HMS1M32M8V
RATING -0.5V to +4.6V -0.5V to +4.6V 8W -65oC to +150oC
Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 3.0V 0 2.0 -0.3*
( TA=0 to 70 o C )
TYP. 3.3V 0 -
MAX 3.6V 0 Vcc+0.3V** 0.8V
VIL(Min.) = -2.0V (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 3.3V 0.3V )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=3.3V, Temp=25 oC TEST CONDITIONS VIN = Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0Ma IOL = 8.0mA SYMBO L ILI IL0 VOH VOL MIN -2 -2 2.4 0.4 MAX 2 2 UNITS A A V V
HANBit Electronics Co.,Ltd.
HANBit DC AND OPERATING CHARACTERISTICS (2)
HMS1M32M8V
MAX DESCRIPTION Power Supply Current:Operating Power Supply Current:Standby TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V SYMBOL lCC lSB lSB1 -12 150 70 20 -15 145 70 20 -20 140 70 20 UNIT mA mA mA
CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN MAX 8 7 UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 3.3V 0.3V, unless otherwise specified)
TEST CONDITIONS
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load
VALUE 0 to 3V 3ns 1.5V See below
Output Load (A) VL=1.5V
Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V
50 DOUT Z0=50 30pF DOUT 353
319 5pF*
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HANBit READ CYCLE
-12 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time Chip Select to Power Down Time
SYMBOL MIN MAX MIN MAX
HMS1M32M8V
-15
MIN
-20
UNIT MAX
tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH tPU tPD
12 12 12 6 0 3 0 0 3 0 12 6 6
15 15 15 7 0 3 0 0 3 0 15 7 7
20 20 20 9 0 3 0 0 3 0 20 9 9
ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE
-12 PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z
SYMBOL MIN MAX MIN MAX MIN MAX
-15
-20
UNIT
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
12 8 0 8 8 0 0 6 0 3 6
15 10 0 10 10 0 0 7 0 3 7
20 12 0 12 12 0 0 9 0 3 9
ns ns ns ns ns ns ns ns ns ns
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HANBit TIMING DIAGRAMS
HMS1M32M8V
TIMING WAVEFORM OF READ CYCLE( Address Controlled)( /CE =/OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE ( /WE = VIH )
tRC Address tAA /CE tLZ(4,5) /OE tOLZ Data Out Vcc Supply Current High-Z
Data Valid
tHZ(3,4,5) tCO tOHZ tOE tOH
lCC lSB
tPU 50%
tPD 50%
Notes (Read Cycle)
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low.
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock )
tWC
Address
tAW tWR(5)
/OE
tCW(3)
/CE
tAS(4) tWP(2)
/WE
tDW tDH Data Valid tOHZ tOW High-Z High-Z
Data In
Data Out
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed)
tWC
Address
tAW tCW(3) tWR(5)
/CE
tAS(4) tOH tWP(2) tDW tDH Data Valid tWHZ(6,7) tOW High-Z(8) (10) (9)
/WE
Data In
High-Z
Data Out
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of wirte. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
PACKAGING DIMMENSIONS
SIMM Design
108.20 mm 3.18 mm TYP(2x)
16 mm 6.35 mm
1
72
2.03 mm 1.02 mm 6.35 mm 95.25 mm 1.27 mm 3.34 mm
0.25 mm MAX
2.54 mm MIN
1.29 mm
Gold : 1.040.10 mm 1.27 Solder : 0.9140.10 mm
(Solder & Gold Plating Lead)
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
ORDERING INFORMATION
1
2
3
4
5
6
7
8
HMS
HANBit Memory Modules SRAM
1M 32 M8V-15
15ns Access Time Component, 3.3V SIMM x32bit 1M
1. - Product Line Identifier HANBit ------------------------------------------------------- H 2. - Memory Modules 3. - SRAM 4. - Depth : 1M 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M ZIP ------------------------------------------------------- Z 7. - Number of Memory Components, 3.3V --------------V 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns
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